The present invention relates to a semiconductor integrated circuit device, such as a dynamic read-and-write memory (hereinafter abbreviated to "DRAM") having a large storage capacity, such as 16 Mb.
Efforts have been made to develop DRAMs having a large storage capacity, such as 16 Mb. One of recently developed DRAMs having such a large storage capacity is published in "Nikkei Microdevices", Nikkei MacGraw-Hill Co., pp. 67-81, Mar. 1, 1988.
Increase in the read cycle time and the write cycle time due to the very narrow wiring lines, very small intervals between the wiring lines and the miniaturized component elements is a problem when forming a DRAM having a large storage capacity in a small IC chip. For example, since the Y-selection lines have a high resistance, the selection of the sense amplifier further from the Y-decoder takes longer time. Since a limited number of narrow wiring lines are available for the peripheral circuit, the wiring lines must be formed along the shortest paths and the uses of the narrow wiring lines must be determined properly according to their resistances. The inventors of the present invention found through the study of DRAMs having a large capacity that newly developed techniques must be employed in addition to the conventional techniques of constructing a conventional 16 Mb DRAM to realize a DRAM having a large storage capacity of 16 Mb and capable of operating at a sufficiently high operating speed.
An invention pertinent to the present invention is disclosed in Japanese Patent Application No. 3-40953.